5 Commits (ac72929574a04facddfd6d7b1db4889daed95206)

Author	SHA1	Message	Date
D.R.racer	2f5dff6c5b	Introduce short namespace aliases ... especially for modules	2021-08-04 11:03:56 +02:00
Alex Voinea	9232e55563	millis interrupt	2021-08-04 10:51:33 +02:00
D.R.racer	6af65bc4c8	Rename ISR -> Isr to avoid clash with AVR libc ISR #define	2021-07-26 09:34:24 +02:00
D.R.racer	c15b1d59c4	Introduce Doxyfile + fix modules documentation	2021-06-30 07:39:31 +02:00
D.R.racer	ede475c5a6	Introduce Timebase module, refactor timing code + unit tests	2021-06-21 10:22:17 +02:00