83 lines
2.3 KiB
C++
83 lines
2.3 KiB
C++
#include "../usart.h"
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#include <avr/interrupt.h>
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namespace hal {
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namespace usart {
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USART usart1;
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uint8_t USART::Read() {
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uint8_t c = 0;
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rx_buf.ConsumeFirst(c);
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return c;
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}
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void USART::Write(uint8_t c) {
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_written = true;
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// If the buffer and the data register is empty, just write the byte
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// to the data register and be done. This shortcut helps
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// significantly improve the effective datarate at high (>
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// 500kbit/s) bitrates, where interrupt overhead becomes a slowdown.
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if (tx_buf.IsEmpty() && (husart->UCSRxA & (1 << 5))) {
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husart->UDRx = c;
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husart->UCSRxA |= (1 << 6);
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return;
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}
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// If the output buffer is full, there's nothing for it other than to
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// wait for the interrupt handler to empty it a bit
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while (!tx_buf.push_back_DontRewrite(c)) {
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if (bit_is_clear(SREG, SREG_I)) {
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// Interrupts are disabled, so we'll have to poll the data
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// register empty flag ourselves. If it is set, pretend an
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// interrupt has happened and call the handler to free up
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// space for us.
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if (husart->UCSRxA & (1 << 5)) {
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ISR_UDRE();
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}
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} else {
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// nop, the interrupt handler will free up space for us
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}
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}
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husart->UCSRxB |= (1 << 5); //enable UDRE interrupt
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}
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void USART::Flush() {
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// If we have never written a byte, no need to flush. This special
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// case is needed since there is no way to force the TXC (transmit
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// complete) bit to 1 during initialization
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if (!_written) {
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return;
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}
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while ((husart->UCSRxB & (1 << 5)) || ~(husart->UCSRxA & (1 << 6))) {
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if (bit_is_clear(SREG, SREG_I) && (husart->UCSRxB & (1 << 5)))
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// Interrupts are globally disabled, but the DR empty
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// interrupt should be enabled, so poll the DR empty flag to
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// prevent deadlock
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if (husart->UCSRxA & (1 << 5)) {
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ISR_UDRE();
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}
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}
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// If we get here, nothing is queued anymore (DRIE is disabled) and
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// the hardware finished tranmission (TXC is set).
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}
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void USART::puts(const char *str) {
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while (*str) {
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Write(*str++);
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}
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}
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} // namespace usart
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} // namespace hal
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ISR(USART1_RX_vect) {
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hal::usart::usart1.ISR_RX();
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}
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ISR(USART1_UDRE_vect) {
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hal::usart::usart1.ISR_UDRE();
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}
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